Index of /srv/backup/AmigaPCI-main/DataSheets/TimingDiagrams/

NameLast ModifiedSizeType
../ -  Directory
Bus Sizing/2025-Aug-15 06:46:24-  Directory
LogicAnalyzer/2025-Aug-15 06:46:24-  Directory
Agnus DMA Timing.pdf2025-Aug-15 01:49:18103.0Kapplication/pdf
CHIP RAM CPU AND DMA READ CYCLES.png2025-Aug-15 01:49:1879.4Kimage/png
CHIP RAM CPU AND DMA READ CYCLES.txt2025-Aug-15 01:49:183.6Ktext/plain;charset=utf-8
CIA Cycle Best Case Read.png2025-Aug-15 01:49:1829.9Kimage/png
CIA Cycle Best Case Write.png2025-Aug-15 01:49:1829.0Kimage/png
CIA Cycle Worst Case Read.png2025-Aug-15 01:49:1832.2Kimage/png
CIA Cycle Worst Case Write.png2025-Aug-15 01:49:1830.4Kimage/png
CIA Cycle.txt2025-Aug-15 01:49:183.7Ktext/plain;charset=utf-8
CPU Chipset RAM Cycle.png2025-Aug-15 01:49:1886.9Kimage/png
CPU Chipset RAM Cycle.txt2025-Aug-15 01:49:183.1Ktext/plain;charset=utf-8
CPU Driven Burst Read Cycle Fast With PCI Wait.png2025-Aug-15 01:49:1848.9Kimage/png
CPU Driven Burst Read Cycle Fast.png2025-Aug-15 01:49:1845.6Kimage/png
CPU Driven Burst Read Fast WITH PCI WAIT.txt2025-Aug-15 01:49:181.4Ktext/plain;charset=utf-8
CPU Driven Burst Read Fast.txt2025-Aug-15 01:49:181.3Ktext/plain;charset=utf-8
Chipset DMA Cycle.png2025-Aug-15 01:49:1866.2Kimage/png
Chipset DMA Cycle.txt2025-Aug-15 01:49:181.8Ktext/plain;charset=utf-8
Chipset Register Cycle.png2025-Aug-15 01:49:1847.9Kimage/png
Chipset Register Cycle.txt2025-Aug-15 01:49:181.8Ktext/plain;charset=utf-8
Fast RAM.png2025-Aug-15 01:49:1859.7Kimage/png
Fast RAM.txt2025-Aug-15 01:49:181.4Ktext/plain;charset=utf-8
IDE Control Reg Read Cycle.txt2025-Aug-15 01:49:181.1Ktext/plain;charset=utf-8
IDE Control Reg Write Cycle.txt2025-Aug-15 01:49:181.1Ktext/plain;charset=utf-8
IDE Control Register Read.png2025-Aug-15 01:49:1843.2Kimage/png
IDE Control Register Write.png2025-Aug-15 01:49:1842.3Kimage/png
IDE Data Register Read.png2025-Aug-15 01:49:1855.6Kimage/png
IDE Data Register Write.png2025-Aug-15 01:49:1851.7Kimage/png
IDE Read Cycle.txt2025-Aug-15 01:49:181.5Ktext/plain;charset=utf-8
IDE Write Cycle.txt2025-Aug-15 01:49:181.5Ktext/plain;charset=utf-8
PCI Burst Cycle Disconnect.png2025-Aug-15 01:49:1872.3Kimage/png
PCI Burst Cycle Disconnect.txt2025-Aug-15 01:49:181.6Ktext/plain;charset=utf-8
PCI Burst DMA Read Cycle With Wait.txt2025-Aug-15 01:49:181.9Ktext/plain;charset=utf-8
PCI Burst DMA Read Cycle.txt2025-Aug-15 01:49:181.8Ktext/plain;charset=utf-8
PCI Burst DMA Write Cycle.txt2025-Aug-15 01:49:181.7Ktext/plain;charset=utf-8
PCI Burst Write Cycle Fast.png2025-Aug-15 01:49:1842.7Kimage/png
PCI Burst Write Cycle Fast.txt2025-Aug-15 01:49:181.3Ktext/plain;charset=utf-8
PCI Burst Write Cycle Wait Fast.png2025-Aug-15 01:49:1844.7Kimage/png
PCI Burst Write Cycle Wait Fast.txt2025-Aug-15 01:49:181.3Ktext/plain;charset=utf-8
PCI Burst Write Cycle Wait.png2025-Aug-15 01:49:1870.4Kimage/png
PCI Burst Write Cycle Wait.txt2025-Aug-15 01:49:181.6Ktext/plain;charset=utf-8
PCI Burst Write Cycle.png2025-Aug-15 01:49:1871.9Kimage/png
PCI Burst Write Cycle.txt2025-Aug-15 01:49:181.7Ktext/plain;charset=utf-8
PCI Config Read Cycle.txt2025-Aug-15 01:49:181.1Ktext/plain;charset=utf-8
PCI Config Write.txt2025-Aug-15 01:49:181.0Ktext/plain;charset=utf-8
PCI Configuration Read Cycle.png2025-Aug-15 01:49:1849.0Kimage/png
PCI Configuration Write Cycle.png2025-Aug-15 01:49:1848.1Kimage/png
PCI Cycle Retry.png2025-Aug-15 01:49:1847.3Kimage/png
PCI Cycle Retry.txt2025-Aug-15 01:49:181.0Ktext/plain;charset=utf-8
PCI DMA Burst Read Cycle With Wait.png2025-Aug-15 01:49:1864.9Kimage/png
PCI DMA Burst Read Cycle.png2025-Aug-15 01:49:1861.9Kimage/png
PCI DMA Burst Write Cycle With Wait.png2025-Aug-15 01:49:1864.5Kimage/png
PCI DMA Burst Write Cycle With Wait.txt2025-Aug-15 01:49:181.9Ktext/plain;charset=utf-8
PCI DMA Burst Write Cycle.png2025-Aug-15 01:49:1857.0Kimage/png
PCI DMA Normal Read Cycle.png2025-Aug-15 01:49:1852.5Kimage/png
PCI DMA Normal Write Cycle.png2025-Aug-15 01:49:1846.9Kimage/png
PCI Normal DMA Read Cycle.txt2025-Aug-15 01:49:181.5Ktext/plain;charset=utf-8
PCI Normal DMA Write Cycle.txt2025-Aug-15 01:49:181.4Ktext/plain;charset=utf-8
PCI Normal Read Cycle2025-Aug-15 01:49:181.1Kapplication/octet-stream
PCI Normal Read Cycle.png2025-Aug-15 01:49:1848.9Kimage/png
PCI Normal Write Cycle2025-Aug-15 01:49:181.2Kapplication/octet-stream
PCI Normal Write Cycle.png2025-Aug-15 01:49:1852.7Kimage/png
ROM Cycle.png2025-Aug-15 01:49:1836.0Kimage/png
ROM Cycle.txt2025-Aug-15 01:49:180.7Ktext/plain;charset=utf-8
lighttpd/1.4.78