{signal: [
  ['Clocks',
  {name: 'C1(CCK)', wave: 'l....h..........l..........h......', "period": 1, "phase": .25},  
  {name: 'C3(CCKQ)', wave: 'l.........h..........l..........h', "period": 1, "phase": -.2}, 
  {name: 'BCLK', wave: 'p................',  "period": 2}],
['Bridge', 
  {name: '_DBDIR', wave: '1.......=......................1..', "period": 1, "phase": 0.5},
 {name: '_DBEN', wave: '1................=.....=......1...', "period": 1, data:['WRITE/READ', 'READ']}],
['Agnus',
  {name: 'RGA0..9', wave: 'x..=...........=..........x.......', "period": 1},
  {name: '_DBR', wave: '1.0.................1.............', "period": 1, "phase": 0.5},
  {name: '_RAS0', wave: '1.........0............1.........',"period": 1, "phase": -0.2},
  {name: '_CASL/U', wave: '1...............0...........1.....',"period": 1, "phase": 0.25},
 {name: '_AWE', wave: '1.......=................1........', "period": 1, "phase": 0.5}],
['SDRAM',
  {name: 'SDRAM D(0..31)', wave: 'z.........................4...z...', "period": 1, data: ['Valid']},
  {name: '_xDQM', wave: '1...............=...........1.....', "period": 1},
  {name: 'SDRAM A0-9', wave: 'x..................=.=.x..........',"period": 1},
  {name: 'SDRAM A10', wave: 'x..................=.1.x..........',"period": 1},
  {name: 'CKE', wave: '1.................................',"period": 1},
  {name: '_CS', wave: '1..................0...1..........',"period": 1},
  {name: '_RAS', wave: '1..................0.1............',"period": 1},
  {name: '_CAS', wave: '1....................0.1..........',"period": 1},
  {name: '_WE', wave: '1....................=.1..........',"period": 1},
  {name: 'SDRAM CMD', wave: '=..................7.5.=..........', "period": 1, data: ['NOP', 'BA', 'RW', 'NOP']}]
], 
 head:{
   text:'CHIPSET DMA RAM CYCLE'
 }, foot:{
   text:'Burst Length = 1. CAS Latency = 2.'
 }, config:{skin:'narrow'}}