{signal: [
  ['Clocks',
  {name: 'C1(CCK)', wave: 'l....h..........l..........h..........l..........h.....', "period": 1, "phase": .25},  
  {name: 'C3(CCKQ)', wave: 'l.........h..........l..........h..........l..........h', "period": 1, "phase": -.2}, 
  {name: 'CLK7', wave: 'p....', "period": 11, "phase": 0.8 },     
  {name: 'BCLK', wave: 'p...........................',  "period": 2}],
['MC68040',  
  {name: 'CLOCK', wave: 'z.....=.=.........................................=.z...',  "period": 1, data:['1', 'W', '2']},
  {name: 'R_W', wave: '1.....=.............................................1...', "period": 1},
  {name: 'A(0..20)', wave: 'z.....=.............................................z...', "period": 1},
 {name: 'D(16..31) (WRITE)', wave: 'z.....=.............................................z...', "period": 1}],
['Controller',
  {name: '_AS', wave: '1.....................0...........................1.....', "period": 1},
  {name: '_REGEN', wave: '1.....................0...........................1.....', "period": 1},
  {name: '_LDS/_UDS', wave: '1.....................=............=..............1.....',"period": 1, data: ['READ','READ/WRITE']},  
  {name: '_TA', wave: 'z.....1..........................................0.1.z..', "period": 1},
  {name: '_TBI', wave: 'z.....1..........................................0.1.z..', "period": 1},
  {name: '_DBEN', wave: '1.......................................................', "period": 1},
  {name: '_DRDEN', wave: '1.......................................................', "period": 1},
  {name: 'LATCH', wave: 'x..........................................3..........x.', "period": 1, data: ['Valid']}],
  ['CS',
  {name: 'DRD(0..15)', wave: 'z......................................4.........z......', "period": 1, "phase": 0.8, data: ['Valid']}]
], 
 head:{
   text:'CPU CHIPSET REGISTER CYCLE',
 }, config:{skin:'narrow'}}