This chapter documents the backend for the Motorola 6800 microprocessor family.

Legal
=====

This module is written in 2013-2016,2021 by Esben Norby and Frank Wille and is covered by the vasm copyright without modifications.

Additional options for this module
==================================

This module provides the following additional options:

-m6800
     Generate code for the 6800 CPU (default setting).

-m6801
     Generate code for the 6801 CPU.

-m68hc11
     Generate code for the 68HC11 CPU.

General
=======

This backend accepts 6800 family instructions for the following CPUs:

  * 6800 code generation: 6800, 6802, 6808.

  * 6801 code generation: 6801, 6803.

  * 68HC11.

The 6804, 6805 and 68HC08 are not supported, they use a similar instruction set, but are not opcode compatible.

The target address type is 16 bit.

Instructions consist of one up to five bytes and require no alignment. There is also no alignment requirement for sections and data.

Extensions
==========

This backend provides the following specific extensions:

  - When an instruction supports direct and extended addressing mode the < character can be used to force direct mode and the > character forces extended mode. Otherwise the assembler selects the best mode automatically, which defaults to extended mode for external symbols.

  - When applying the operation /256, %256 or &256 on a label, an appropriate lo/hi-byte relocation will automatically be generated.

Optimizations
=============

None.

Known Problems
==============

Some known problems of this module at the moment:

  - None?

Error Messages
==============

This module has the following error messages:

  - 2001: trailing garbage in operand

  - 2002: data size %d not supported

  - 2003: operand doesn't fit into 8-bits

  - 2004: branch destination out of range