This chapter documents the backend for the 8080/z80/gbz80/64180/RCMx000 microprocessor family.

Legal
=====

This module is copyright in 2009 by Dominic Morris.

     Redistribution and use in source and binary forms, with or without
     modification, are permitted provided that the following conditions
     are met:
     1. Redistributions of source code must retain the above copyright
        notice, this list of conditions and the following disclaimer.
     2. Redistributions in binary form must reproduce the above copyright
        notice, this list of conditions and the following disclaimer in the
        documentation and/or other materials provided with the distribution.

     THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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     THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Additional options for this module
==================================

This module provides the following additional options:

-8080
     Turns on 8080/8085 compatibility mode. Any use of z80 (or higher) opcodes will result in an error being generated.

-gbz80
     Turns on gbz80 compatibility mode. Any use of non-supported opcodes will result in an error being generated.

-hd64180
     Turns on 64180 mode supporting additional 64180 opcodes.

-intel-syntax
     Turns on the older Intel 8080 syntax mode.  When this mode is activated, mnemonics and operand types from the Intel 8080 syntax instead of the Zilog Z80 syntax (such as STA 1234h instead of ld (1234h),a) will be valid.  This option can be used in parallel with -8080 to use both sets of mnemonics, although this is discouraged, as two instructions (jp and cp) mean different things in each syntax. In this case, these instructions will be assembled as the Intel syntax, and a warning will be emitted.

-rcm2000

-rcm3000

-rcm4000
     Turns on Rabbit compatibility mode, generating the correct codes for moved opcodes and supporting the additional Rabbit instructions. In this mode, 8 bit access to the 16 bit index registers is not permitted.

-rcmemu
     Turns on emulation of some instructions which aren't available on the Rabbit processors.

-swapixiy
     Swaps the usage of ix and iy registers. This is useful for compiling generic code that uses an index register that is reserved on the target machine.

-z80asm
     Switches on z80asm mode. This translates ASMPC to $ and accepts some pseudo opcodes that z80asm supports. Most emulation of z80asm directives is provided by the oldsyntax syntax module.

General
=======

This backend accepts z80 family instructions in standard Zilog syntax. Rabbit opcodes are accepted as defined in the publicly available reference material from Rabbit Semiconductor, with the exception that the ljp and lcall opcodes need to be supplied with a 24 bit number rather than an 8 bit xpc and a 16 bit address.

The target address type is 16 bit.

Instructions consist of one up to six bytes and require no alignment. There is also no alignment requirement for sections and data.

The current PC symbol is $.

Extensions
==========

This backend provides the following specific extensions:

  - Certain Rabbit opcodes can be prefixed by the altd and/or the ioi/ioe modifier. For details of which instructions these are valid for please see the documentation from Rabbit.

  - The parser understands a lo/hi-modifier to select low- or high-byte of a 16-bit word. The character < is used to select the low-byte and > for the high-byte. It has to be the first character before an expression.

  - When applying the operation /256, %256 or &255 on a label, an appropriate lo/hi-byte relocation will automatically be generated.

Optimisations
=============

This backend supports the emulation of certain z80 instructions on the Rabbit/gbz80 processor. These instructions are rld, rrd, cpi, cpir, cpd and cpdr. The link stage should provide routines with the opcode name prefixed with rcmx_ (eg rcmx_rld) which implements the same functionality. Example implementations are available within the z88dk CVS tree.

Additionally, for the Rabbit targets the missing call cc, opcodes will be emulated.

Known Problems
==============

Some known problems of this module at the moment:

  - Not all RCM4000 opcodes are supported (llcall, lljp are not available).

Error Messages
==============

This module has the following error messages:

  - 2001: trailing garbage in operand

  - 2002: Opcode not supported by %s (%s)

  - 2003: Index registers not available on 8080

  - 2004: out of range for 8 bit expression (%d)

  - 2005: invalid bit number (%d) should be in range 0..7

  - 2006: rst value out of range (%d/0x%02x)

  - 2007: %s value out of range (%d)

  - 2008: index offset should be a constant

  - 2009: invalid branch type for jr

  - 2010: Rabbit target doesn't support rst %d

  - 2011: Rabbit target doesn't support 8 bit index registers

  - 2012: z180 target doesn't support 8 bit index registers

  - 2013: invalid branch type for jre

  - 2014: Opcode not supported by %s (%s) but it can be emulated (-rcmemu)

  - 2015: %s specifier is only valid for Rabbit processors

  - 2016: Only one of ioi and ioe can be specified at a time

  - 2017: %s specifier is not valid for the opcode %s

  - 2018: %s specifier redundant for the opcode %s

  - 2019: %s specifier has no effect on the opcode %s

  - 2020: Operand value must evaluate to a constant for opcode %s

  - 2021: Unhandled operand type wanted 0x%x got 0x%x

  - 2022: Missed matched index registers on %s

  - 2023: Only out (c),0 is supported for the opcode %s

  - 2024: Operations between different index registers are forbidden

  - 2025: Operations between ix/iy/hl are forbidden

  - 2026: Double indirection forbidden

  - 2027: Instruction %s will be assembled as '%s'

  - 2028: index offset out of bounds (%d)