This chapter documents the backend for the PDP-11 CPU architecture.

Legal
=====

This module is written in 2020 by Frank Wille and is covered by the vasm copyright without modifications.

Additional options for this module
==================================

This module provides the following additional options:

-eis
     Enables the Extended Instruction Set option (EIS).

-fis
     Enables the Floating point Instruction Set option (FIS).

-msp
     Enables additional memory space instructions.

-opt-branch
     Enables optimization of jmp instructions to br when possible and translates br instructions to jmp when required. It will also translate conditional branches, where the destination is out of range, into a jmp instruction and a negated conditional branch over this jmp.

General
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This backend accepts PDP-11 instructions as described in the PDP11/40 Processor Handbook, by Digital Equipment Corporation.

The target address type is 16 bit.

Instructions consist of two up to six bytes and required 16-bit alignment. Data, when not accessed as single bytes, also requires 16-bit alignment.

Known Problems
==============

Some known problems of this module at the moment:

  - Doesn't support all PDP-11 extensions.

Error Messages
==============

This module has the following error messages:

  - 2001: bad addressing mode

  - 2002: bad register

  - 2003: pc-relative destination out of range: %ld (valid: %d..%d)

  - 2004: bad trap code %ld (valid: %d..%d)

  - 2005: displacement out of range: %ld

  - 2006: immediate value out of range: %ld

  - 2007: absolute address out of range: %ld

  - 2008: data size %d not supported

  - 2009: data expression doesn't fit into %d bits